Power modeling for high-level power estimation

In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional (4-D) table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient, and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an rms error of about 4% and average error of about 6%. Except for one out of about 10 000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the rms error becomes under 1%, the average error becomes under 5%, and the largest error observed in all cases is under 18%.